LTspice IV:Stability of Opamp Circuits

What people said

Recommends KarlKarlsom · 2021-03 · Electrical Engineering Stack Exchange · on “Circuit stable in the Bode diagram, unstable in step-response”

[this video] - this could help you - it does not explain the "why" you need to measure the phase.margin at open loop gain, but the "how" in LtSpice

Cites Ryan · 2015-02 · Electrical Engineering Stack Exchange · on “how do I stabilize opamp amplifier oscillation”

Ok, so I followed this tutorial, and it's a bit different to what you explained - they use an open loop and put the voltage at the inverting output [this video] it gave me this result: [LINK] -125 degrees phase margin

Cites Big6 · 2018-07 · Electrical Engineering Stack Exchange · on “LF356 integrator simulation using LTspice”

I have seen similar issues in the past with LTspice and from my experience it comes down to the dc operating point. Let's take a look. This is your circuit: [LINK] Look at the dc operating point of the output (~13V) (red box in the picture), essentially saturating and not in the linear region anymore. Even though, your input source has 0 Vdc, you still amplify some dc signal—that is the offset voltage . For the LF356 this is spec'd at 10mV and this is being amplified by the huge dc gain of the circuit. This messes up the dc operating point and you no longer have meaningful results. To have meaningful results, you want the dc operating point of both the input and output to be about the same—a

Cites Vinlar · 2019-08 · Electrical Engineering Stack Exchange · on “Op-amp circuit stability (LTspice)”

I want to study the stability of my op-amp circuit with LTspice. I found this video as tutorial: tutorial on phase margin [this video] I did the simulation with closed and open loop as suggested and got the following plots: Closed loop: [LINK] And in open-loop as used in the video tutorial: [LINK] How to read those plots and conclude if my circuit is stable or not? 0.3 V pulse response: [LINK] Open loop chart with view of 0 dB point: [LINK]

Cites fuad1502 · 2020-03 · Electrical Engineering Stack Exchange · on “The Effect of Input and Feedback Capacitors on an Operational Amplifier Open-Loop Gain Response”

I have the following circuit that I want to compensate: [LINK] As shown from the step response, the circuit is unstable because of the high input capacitance (the green plot is without any additional input capacitance, while the blue plot is with the 520 pF input capacitance connected). I plotted the open-loop gain AC response to calculate the phase margin: [LINK] As can be seen from the plot above, the phase margin is around 0 degrees. Comparing between the blue and green plot also shows the additional pole caused by the 520 pF input capacitance at around 600 kHz (This cutoff frequency is exactly as calculated with the equation shown after the following paragraph). As a note, to acquire the

Cites Confused · 2023-12 · Electrical Engineering Stack Exchange · on “LTspice IV: Stability of op-amp circuits”

I am studying the stability of op-amp circuits using LTspice with the help of this video [this video] . I can see many threads on Stack Exchange like this one [LINK] , but the explanation is not clear to me. I have a couple of questions regarding this. For checking the gain peaking, the loop is not broken. Why is the phase margin not available from that gain peaking plot? For finding the PM, the loop is broken and a source is placed with DC = 0 and AC = 1. Why? What will happen if I provide some other value like DC = 5 V instead of DC = 0? Can I break the loop anywhere? Is there any method to test the stability without breaking the loop? In both cases (gain peaking and PM) the input source is mad

Cites user319836 · 2024-06 · Electrical Engineering Stack Exchange · on “LTSpice simulation produced different results of phase margin when using step-signal % overshoot technique vs loop analysis technique”

I spent some time with this and can now provide a better answer. I will leave the existing discussion for comparison. In the video by LT [this video] , the first attempt to stabilize the capacitive load was a series resistor with the capacitor. Only then was the feedback compensation applied. I chose a series resistor also to damp the oscillations, but I knew at the time it was not power efficient. A better choice for an inductor is a parallel resistor. This will allow the resistor to dominate high frequencies and the inductor dominate the low frequencies. So I start there without the U1 feedback capacitor and the 1k feedback resistor set to zero. R4 is stepped through 3 values in a transient ana

Cites Zhi · 2024-06 · Electrical Engineering Stack Exchange · on “LTSpice simulation produced different results of phase margin when using step-signal % overshoot technique vs loop analysis technique”

I am working on a class AB amplifier circuit to that can output both AC and DC current, controlled by an op-amp with feedback from the final output. The output will be driving an 50uH inductor. [LINK] The inductor introduced instability into the system, which I am trying to over come with C1 and R4. I then used the technique introduced by this video by LT [this video] to get the simulated phase margin: Modified circuit to use the technique in the video: [LINK] Result: [LINK] The phase-shift at ~0 dB is ~ 99 degrees. This equals to phase margin of 99 degrees (right?) To confirm the result is correct, I simulated the same circuit with a different technique, by applying a step signal (10 mV) at the

Cites Designalog · 2024-10 · Electrical Engineering Stack Exchange · on “Stability analysis in LTspice breaks down with biased non-inverting input”

The Issues In Your Simulation Setup There are 2 issues in your simulation setup: Bias voltage in the (+) terminal is too high that it causes the op-amp to saturate -> spoiled operating point. The injection of an AC signal at the output node for loop gain simulation purposes via the LC method requires a replica circuit. About the bias voltage 100mV in that V3 times your gain would already give you the 10V towards the output, and that's probably not even possible even if the opamp is rail-to-rail. Your amplifier is being driven out of its linear region About the LC method and the need for a replica circuit The reason for the huge capacitor is to prevent the voltage source disturbing the DC. Th

Cites FreddaH · 2024-10 · Electrical Engineering Stack Exchange · on “Stability analysis in LTspice breaks down with biased non-inverting input”

I've been playing around with stability analysis in LTspice using the large L and C method. I've noticed that the simulation breaks down with a small bias voltage on the non-inverting input. Changing from a dual supply to a single supply may also break the analysis and it seems to be dependent on the opamp SPICE model as well. I don't have a full understanding of the large L and C method so I might be missing something. Do I need to connect the non-inverting input to ground? What are the mandatory prerequisites for successfully performing a stability analysis with this method? Below are the test circuit I've used and analysis waveforms for 0 V bias and 1 V bias. Edit: I should have plotted V