The Mill CPU Architecture - the Belt (2 of 13)
Why Hacker News recommends it
HN points to the Mill talks as an excellent, deep look at an unconventional CPU design, especially in threads on registers and instruction sets.
What it is
The second talk in the Mill CPU series by Mill Computing, covering the Belt, the Mill's operand-passing model that replaces general registers. It explains the cost of register renaming in conventional wide CPUs and how the Belt reaches high instruction-level parallelism.
Recommended by 1 HN commenters across 1 different months, 2013 to 2023.
What Hacker News said
Recommends wood_spirit · 2023-12 · on “Clockhands: Rename-Free Instruction Set Architecture for Out-of-Order Processors”
This is reminiscent of the Mill CPU which had temporal addressing and called the history a “belt”. the Mill was described in an excellent series of talks: [this video]
Cites mtrimpe · 2013-08 · on “Smalltalk runtime in the browser”
The Mill CPU [1] that was discussed a while ago is quite close to being the perfect architecture for a Lisp though, so hopefully many of other parts of these ideas will also come back in even more impressive forms. [1] [this video]
Cites brigade · 2013-10 · on “Why Registers Are Fast and RAM Is Slow”
The studies would vary over time because CPU design and bottle necks have changed. Early designs were of course limited by transistor count, now we have OoOe and physical registers are limited by muxers and latency (see the presentations by the mill CPU guy [1] Saving registers in functions is mostly irrelevant - you only save what you'd use, so saving more means fewer spills within the function. Saving on context switches (interrupts alone aren't a big deal) was indeed a problem back when AltiVec was designed, thus it has a special register to keep track of which registers need to be saved. In modern designs this is less of a problem, between higher frequencies, multiple cores, and the othe
Cites runeks · 2015-02 · on “64-bit Linux Return-Oriented Programming”
How far has development come with the Mill CPU? This video[1] mentions that "nothing with pins on the bottom" has been made yet. [1] [this video]
Cites w0000t · 2015-08 · on “What's new in CPUs since the 80s and how does it affect programmers?”
No ordinary registers. Instead you have a FIFO queue( belt ), where every element( register ) is accessible and has a relative address( offset ). [this video]
Cites w0000t · 2015-08 · on “What's new in CPUs since the 80s and how does it affect programmers?”
False. Mill does not do register renaming. ( Or use "lies". I failed to comprehend you second sentence. ) Here is a talk from one of the designers explaining how it is done: [this video]
Critical riazrizvi · 2017-01 · on “Mill Computing in 2017”
According to the CTO, 80% of software operations are loops ( [this video] )? I need convincing of that before I watch the rest of the talk. I suspect it would be a fundamental premise for the architecture of the chip. If it's not true, the stats are probably skewed for an unusual benchmark.